To facilitate debug operations, many current integrated circuits (ICs) include Joint Test Action Group (JTAG) compliant circuitry (standardized as IEEE 1149.1 Standard Test Access Port and Boundary-Scan Architecture). JTAG-compliant circuitry and methods of using the circuitry in testing an IC (collectively referred to simply as “JTAG”) provides access to internal blocks of an IC, making JTAG particularly well suited for debugging embedded systems. More particularly, in a device that supports JTAG-compliant boundary scan technology, signals between the device's core logic and the device's pins are intercepted by boundary scan cells, which are coupled together to form a serial scan path known as the boundary scan register (BSR). Normally, the boundary scan cells do not affect IC operations. In test mode, however, the boundary scan cells may be used to set and/or read values. For example, JTAG may be used to manipulate the external interface to an IC's BSR in order to test for certain types of faults (e.g., shorts, opens, and logic faults).
When implemented on an IC, JTAG-compliant circuitry includes, at least, a JTAG interface and a controller with access to an instruction register and a plurality of data registers. The JTAG interface (collectively known as a test access port, or TAP) is either a four-interconnect or a five-interconnect interface. The four primary interconnects include: TMS (test mode state); TCK (clock); TDI (test data in); and TDO (test data out). The JTAG interface may include an extra interconnect when a TRST (test reset) interconnect is implemented. A test reset signal provided via a TRST interconnect may cause a corresponding test reset circuit to generate a system level reset, in an embodiment.
To communicate with a JTAG interface, a host computer may be connected to a target IC's JTAG interface (e.g., through a JTAG adaptor), and the host computer may cause signals to be provided to or read from the JTAG interface. More particularly, the host computer communicates with an IC's TAP controller by manipulating signals on TMS and TDI in conjunction with clocking signals on TCK, and by reading signals presented by the IC on TDO. The state of the TAP controller may change on TCK transitions.
In some multiple-IC systems, such as a system-in-package (SiP), there may be an insufficient number of available package pins to support dedicated, external JTAG interface pins for each IC of the system. Some of these systems may include a single set of external JTAG interface pins that connect, either directly or indirectly, with the JTAG interfaces of the various ICs. In order to test one of the ICs, all ICs except for the IC under tested are set into a “TDI-to-TDO bypass” mode (i.e., a mode in which the IC's TDI and TDO interconnects are essentially directly connected through a TDI-to-TDO bypass register of the IC). In such a configuration, the TDI signals presented at the external TDI pin are passed to the IC under test, and the TDO signals produced by the IC under test appear at the external TDO pin.
For example, FIG. 1 illustrates a simplified circuit diagram 100 of a plurality of ICs 102, 103, 104 with their JTAG TDO and TDI interconnects daisy-chained together, in accordance with the prior art. In the illustrated configuration, access to all of the ICs 102-104 may be provided through a single, external JTAG interface 110. The TMS pin 112 and TCK pin 114 are directly connected to the TMS and TCK interconnects of each IC 102-104, and the TDI and TDO interconnects are daisy-chained together. In other words, the TDI interconnect of a first IC 102 is directly connected to the external TDI pin 116, the TDO interconnect of the first IC 102 is connected to the TDI interconnect of the second IC 103, the TDO interconnect of the second IC 103 is connected to the TDI interconnect of the third IC 104, and the TDO interconnect of the third IC 104 is directly connected to the external TDO pin 118.
To test any one of the ICs (e.g., IC 104), the other ICs (e.g., ICs 102, 103) are set into TDI-to-TDO bypass mode (e.g., by clocking in a BYPASS instruction). The clock input is provided at the TCK pin 114, and clocking changes on the TMS pin 112 step through a standardized JTAG state machine implemented in each of the ICs TAP controllers (not illustrated). In the Shift_IR and Shift_DR states, one bit of data may be transferred from the TDI pin 116 into and out of each tap controller instruction or data register (also not illustrated), respectively, in conjunction with each TCK clock pulse. For example, typical instructions might include: reading or writing data to a data register (e.g., the BSR, TDI-to-TDO bypass register, or the IDCODE register); sampling input pins; driving (or floating) output pins; and so on. Although all of the ICs 102-104 operate in lockstep, only the IC under test (i.e., the IC that is not in TDI-to-TDO bypass mode) is affected by the input signal on the external TDI pin 116 in order to produce valid test data on its TDO port. That valid test data, in turn, is produced at the external TDO pin 118.